- else if (model == TLS_MODEL_LOCAL_DYNAMIC)
- {
-- r3 = gen_rtx_REG (Pmode, 3);
- tga = rs6000_tls_get_addr ();
- tmp1 = gen_reg_rtx (Pmode);
-- emit_library_call_value (tga, tmp1, LCT_CONST, Pmode, 1, r3, Pmode);
-+ emit_library_call_value (tga, tmp1, LCT_CONST, Pmode,
-+ 1, const0_rtx, Pmode);
-
-+ r3 = gen_rtx_REG (Pmode, 3);
- if (DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
- insn = gen_tls_ld_aix64 (r3, got, tga, const0_rtx);
- else if (DEFAULT_ABI == ABI_AIX && !TARGET_64BIT)
-@@ -6694,7 +6696,7 @@
-
- /* Nonzero if we can use an AltiVec register to pass this arg. */
- #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
-- ((ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE)) \
-+ (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
- && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
- && TARGET_ALTIVEC_ABI \
- && (NAMED))
-@@ -6920,7 +6922,7 @@
- existing library interfaces.
-
- Doubleword align SPE vectors.
-- Quadword align Altivec vectors.
-+ Quadword align Altivec/VSX vectors.
- Quadword align large synthetic vector types. */
-
- int
-@@ -6937,7 +6939,7 @@
- && int_size_in_bytes (type) >= 8
- && int_size_in_bytes (type) < 16))
- return 64;
-- else if ((ALTIVEC_VECTOR_MODE (mode) || VSX_VECTOR_MODE (mode))
-+ else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
- || (type && TREE_CODE (type) == VECTOR_TYPE
- && int_size_in_bytes (type) >= 16))
- return 128;
-@@ -7082,8 +7084,7 @@
- cum->nargs_prototype--;
-
- if (TARGET_ALTIVEC_ABI
-- && (ALTIVEC_VECTOR_MODE (mode)
-- || VSX_VECTOR_MODE (mode)
-+ && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
- || (type && TREE_CODE (type) == VECTOR_TYPE
- && int_size_in_bytes (type) == 16)))
- {
-@@ -7677,8 +7678,7 @@
- else
- return gen_rtx_REG (mode, cum->vregno);
- else if (TARGET_ALTIVEC_ABI
-- && (ALTIVEC_VECTOR_MODE (mode)
-- || VSX_VECTOR_MODE (mode)
-+ && (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
- || (type && TREE_CODE (type) == VECTOR_TYPE
- && int_size_in_bytes (type) == 16)))
- {
-@@ -18280,7 +18280,7 @@
-
- /* Some cases that need register indexed addressing. */
- if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
-- || (TARGET_VSX && VSX_VECTOR_MODE (mode))
-+ || (TARGET_VSX && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
- || (TARGET_E500_DOUBLE && mode == DFmode)
- || (TARGET_SPE_ABI
- && SPE_VECTOR_MODE (mode)
-@@ -25565,14 +25565,13 @@
- else if (TREE_CODE (valtype) == COMPLEX_TYPE
- && targetm.calls.split_complex_arg)
- return rs6000_complex_function_value (mode);
-+ /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
-+ return register is used in both cases, and we won't see V2DImode/V2DFmode
-+ for pure altivec, combine the two cases. */
- else if (TREE_CODE (valtype) == VECTOR_TYPE
- && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
-- && ALTIVEC_VECTOR_MODE (mode))
-+ && ALTIVEC_OR_VSX_VECTOR_MODE (mode))
- regno = ALTIVEC_ARG_RETURN;
-- else if (TREE_CODE (valtype) == VECTOR_TYPE
-- && TARGET_VSX && TARGET_ALTIVEC_ABI
-- && VSX_VECTOR_MODE (mode))
-- regno = ALTIVEC_ARG_RETURN;
- else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
- && (mode == DFmode || mode == DCmode
- || mode == TFmode || mode == TCmode))
-@@ -25611,12 +25610,12 @@
- && TARGET_HARD_FLOAT && TARGET_FPRS
- && ((TARGET_SINGLE_FLOAT && mode == SFmode) || TARGET_DOUBLE_FLOAT))
- regno = FP_ARG_RETURN;
-- else if (ALTIVEC_VECTOR_MODE (mode)
-+ /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
-+ return register is used in both cases, and we won't see V2DImode/V2DFmode
-+ for pure altivec, combine the two cases. */
-+ else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode)
- && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
- regno = ALTIVEC_ARG_RETURN;
-- else if (VSX_VECTOR_MODE (mode)
-- && TARGET_VSX && TARGET_ALTIVEC_ABI)
-- regno = ALTIVEC_ARG_RETURN;
- else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
- return rs6000_complex_function_value (mode);
- else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
-
-Zmiany atrybutów dla: gcc/config/rs6000/rs6000.c
-___________________________________________________________________
-Dodane: svn:mergeinfo
- Połączono zmiany /trunk/gcc/config/rs6000/rs6000.c:r162404,173624
-
-Index: gcc/config/rs6000/rs6000.h
-===================================================================
---- gcc/config/rs6000/rs6000.h (.../tags/gcc_4_5_3_release) (wersja 173771)
-+++ gcc/config/rs6000/rs6000.h (.../branches/gcc-4_5-branch) (wersja 173771)
-@@ -1038,10 +1038,9 @@
-
- /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate
- enough space to account for vectors in FP regs. */
--#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
-- (TARGET_VSX \
-- && ((MODE) == VOIDmode || VSX_VECTOR_MODE (MODE) \
-- || ALTIVEC_VECTOR_MODE (MODE)) \
-+#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
-+ (TARGET_VSX \
-+ && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \
- && FP_REGNO_P (REGNO) \
- ? V2DFmode \
- : choose_hard_reg_mode ((REGNO), (NREGS), false))
-@@ -1057,25 +1056,16 @@
- ((MODE) == V4SFmode \
- || (MODE) == V2DFmode) \
-
--#define VSX_SCALAR_MODE(MODE) \
-- ((MODE) == DFmode)
--
--#define VSX_MODE(MODE) \
-- (VSX_VECTOR_MODE (MODE) \
-- || VSX_SCALAR_MODE (MODE))
--
--#define VSX_MOVE_MODE(MODE) \
-- (VSX_VECTOR_MODE (MODE) \
-- || VSX_SCALAR_MODE (MODE) \
-- || ALTIVEC_VECTOR_MODE (MODE) \
-- || (MODE) == TImode)
--
- #define ALTIVEC_VECTOR_MODE(MODE) \
- ((MODE) == V16QImode \
- || (MODE) == V8HImode \
- || (MODE) == V4SFmode \
- || (MODE) == V4SImode)
-
-+#define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \
-+ (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \
-+ || (MODE) == V2DImode)
-+
- #define SPE_VECTOR_MODE(MODE) \
- ((MODE) == V4HImode \
- || (MODE) == V2SFmode \
-@@ -1118,10 +1108,10 @@
- ? ALTIVEC_VECTOR_MODE (MODE2) \
- : ALTIVEC_VECTOR_MODE (MODE2) \
- ? ALTIVEC_VECTOR_MODE (MODE1) \
-- : VSX_VECTOR_MODE (MODE1) \
-- ? VSX_VECTOR_MODE (MODE2) \
-- : VSX_VECTOR_MODE (MODE2) \
-- ? VSX_VECTOR_MODE (MODE1) \
-+ : ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \
-+ ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \
-+ : ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \
-+ ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \
- : 1)
-
- /* Post-reload, we can't use any new AltiVec registers, as we already
-
-Zmiany atrybutów dla: gcc/config/rs6000/rs6000.h
-___________________________________________________________________
-Dodane: svn:mergeinfo
- Połączono zmiany /trunk/gcc/config/rs6000/rs6000.h:r162404,173624
-
-Index: gcc/config/arm/arm.c
-===================================================================
---- gcc/config/arm/arm.c (.../tags/gcc_4_5_3_release) (wersja 173771)
-+++ gcc/config/arm/arm.c (.../branches/gcc-4_5-branch) (wersja 173771)
-@@ -18237,7 +18237,7 @@
- rtx tmp1 = gen_reg_rtx (mode);
- rtx tmp2 = gen_reg_rtx (mode);
-
-- emit_insn (intfn (tmp1, op1, tmp2, op2));
-+ emit_insn (intfn (tmp1, op1, op2, tmp2));
-
- emit_move_insn (mem, tmp1);
- mem = adjust_address (mem, mode, GET_MODE_SIZE (mode));
-Index: gcc/config/arm/neon.md
-===================================================================
---- gcc/config/arm/neon.md (.../tags/gcc_4_5_3_release) (wersja 173771)
-+++ gcc/config/arm/neon.md (.../branches/gcc-4_5-branch) (wersja 173771)
-@@ -680,7 +680,7 @@
- (match_operand:SI 2 "immediate_operand" "i")))]
- "TARGET_NEON"
- {
-- int elt = ffs ((int) INTVAL (operands[2]) - 1);
-+ int elt = ffs ((int) INTVAL (operands[2])) - 1;
- if (BYTES_BIG_ENDIAN)
- elt = GET_MODE_NUNITS (<MODE>mode) - 1 - elt;
- operands[2] = GEN_INT (elt);
-@@ -3895,13 +3895,14 @@
-
- (define_insn "neon_vtrn<mode>_internal"
- [(set (match_operand:VDQW 0 "s_register_operand" "=w")
-- (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")]
-- UNSPEC_VTRN1))
-- (set (match_operand:VDQW 2 "s_register_operand" "=w")
-- (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")]
-- UNSPEC_VTRN2))]
-+ (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
-+ (match_operand:VDQW 2 "s_register_operand" "w")]
-+ UNSPEC_VTRN1))
-+ (set (match_operand:VDQW 3 "s_register_operand" "=2")
-+ (unspec:VDQW [(match_dup 1) (match_dup 2)]
-+ UNSPEC_VTRN2))]
- "TARGET_NEON"
-- "vtrn.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
-+ "vtrn.<V_sz_elem>\t%<V_reg>0, %<V_reg>3"
- [(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
- (const_string "neon_bp_simple")
-@@ -3921,13 +3922,14 @@
-
- (define_insn "neon_vzip<mode>_internal"
- [(set (match_operand:VDQW 0 "s_register_operand" "=w")
-- (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")]
-- UNSPEC_VZIP1))
-- (set (match_operand:VDQW 2 "s_register_operand" "=w")
-- (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")]
-- UNSPEC_VZIP2))]
-+ (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
-+ (match_operand:VDQW 2 "s_register_operand" "w")]
-+ UNSPEC_VZIP1))
-+ (set (match_operand:VDQW 3 "s_register_operand" "=2")
-+ (unspec:VDQW [(match_dup 1) (match_dup 2)]
-+ UNSPEC_VZIP2))]
- "TARGET_NEON"
-- "vzip.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
-+ "vzip.<V_sz_elem>\t%<V_reg>0, %<V_reg>3"
- [(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
- (const_string "neon_bp_simple")
-@@ -3947,13 +3949,14 @@
-
- (define_insn "neon_vuzp<mode>_internal"
- [(set (match_operand:VDQW 0 "s_register_operand" "=w")
-- (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")]
-+ (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")
-+ (match_operand:VDQW 2 "s_register_operand" "w")]
- UNSPEC_VUZP1))
-- (set (match_operand:VDQW 2 "s_register_operand" "=w")
-- (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")]
-- UNSPEC_VUZP2))]
-+ (set (match_operand:VDQW 3 "s_register_operand" "=2")
-+ (unspec:VDQW [(match_dup 1) (match_dup 2)]
-+ UNSPEC_VUZP2))]
- "TARGET_NEON"
-- "vuzp.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
-+ "vuzp.<V_sz_elem>\t%<V_reg>0, %<V_reg>3"
- [(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
- (const_string "neon_bp_simple")
-Index: gcc/config/pa/predicates.md
-===================================================================
---- gcc/config/pa/predicates.md (.../tags/gcc_4_5_3_release) (wersja 173771)
-+++ gcc/config/pa/predicates.md (.../branches/gcc-4_5-branch) (wersja 173771)
-@@ -411,12 +411,16 @@
-
- ;; True iff depi can be used to compute (reg | OP).
-
--(define_predicate "ior_operand"
-- (match_code "const_int")
--{
-- return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
--})
-+(define_predicate "cint_ior_operand"
-+ (and (match_code "const_int")
-+ (match_test "ior_mask_p (INTVAL (op))")))
-
-+;; True iff OP can be used to compute (reg | OP).
-+
-+(define_predicate "reg_or_cint_ior_operand"
-+ (ior (match_operand 0 "register_operand")
-+ (match_operand 0 "cint_ior_operand")))
-+
- ;; True iff OP is a CONST_INT of the forms 0...0xxxx or
- ;; 0...01...1xxxx. Such values can be the left hand side x in (x <<
- ;; r), using the zvdepi instruction.
-Index: gcc/config/pa/pa.md
-===================================================================
---- gcc/config/pa/pa.md (.../tags/gcc_4_5_3_release) (wersja 173771)
-+++ gcc/config/pa/pa.md (.../branches/gcc-4_5-branch) (wersja 173771)
-@@ -5686,7 +5686,7 @@
- (define_expand "iordi3"
- [(set (match_operand:DI 0 "register_operand" "")
- (ior:DI (match_operand:DI 1 "register_operand" "")
-- (match_operand:DI 2 "ior_operand" "")))]
-+ (match_operand:DI 2 "reg_or_cint_ior_operand" "")))]
- ""
- "
- {
-@@ -5707,7 +5707,7 @@
- (define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=r,r")
- (ior:DI (match_operand:DI 1 "register_operand" "0,0")
-- (match_operand:DI 2 "ior_operand" "M,i")))]
-+ (match_operand:DI 2 "cint_ior_operand" "M,i")))]
- "TARGET_64BIT"
- "* return output_64bit_ior (operands); "
- [(set_attr "type" "binary,shift")
-@@ -5726,19 +5726,14 @@
- (define_expand "iorsi3"
- [(set (match_operand:SI 0 "register_operand" "")
- (ior:SI (match_operand:SI 1 "register_operand" "")
-- (match_operand:SI 2 "arith32_operand" "")))]
-+ (match_operand:SI 2 "reg_or_cint_ior_operand" "")))]
- ""
-- "
--{
-- if (! (ior_operand (operands[2], SImode)
-- || register_operand (operands[2], SImode)))
-- operands[2] = force_reg (SImode, operands[2]);
--}")
-+ "")
-
- (define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=r,r")
- (ior:SI (match_operand:SI 1 "register_operand" "0,0")
-- (match_operand:SI 2 "ior_operand" "M,i")))]
-+ (match_operand:SI 2 "cint_ior_operand" "M,i")))]
- ""
- "* return output_ior (operands); "
- [(set_attr "type" "binary,shift")
-Index: gcc/config/pa/pa-protos.h
-===================================================================
---- gcc/config/pa/pa-protos.h (.../tags/gcc_4_5_3_release) (wersja 173771)
-+++ gcc/config/pa/pa-protos.h (.../branches/gcc-4_5-branch) (wersja 173771)
-@@ -79,7 +79,6 @@
- extern int prefetch_cc_operand (rtx, enum machine_mode);
- extern int prefetch_nocc_operand (rtx, enum machine_mode);
- extern int and_operand (rtx, enum machine_mode);
--extern int ior_operand (rtx, enum machine_mode);
- extern int arith32_operand (rtx, enum machine_mode);
- extern int uint32_operand (rtx, enum machine_mode);
- extern int reg_before_reload_operand (rtx, enum machine_mode);
-@@ -94,7 +93,6 @@
- extern int fmpyaddoperands (rtx *);
- extern int fmpysuboperands (rtx *);
- extern int call_operand_address (rtx, enum machine_mode);
--extern int ior_operand (rtx, enum machine_mode);
- extern void emit_bcond_fp (rtx[]);
- extern int emit_move_sequence (rtx *, enum machine_mode, rtx);
- extern int emit_hpdiv_const (rtx *, int);
-Index: libffi/src/alpha/osf.S
-===================================================================
---- libffi/src/alpha/osf.S (.../tags/gcc_4_5_3_release) (wersja 173771)
-+++ libffi/src/alpha/osf.S (.../branches/gcc-4_5-branch) (wersja 173771)
-@@ -1,5 +1,5 @@
- /* -----------------------------------------------------------------------
-- osf.S - Copyright (c) 1998, 2001, 2007, 2008 Red Hat
-+ osf.S - Copyright (c) 1998, 2001, 2007, 2008, 2011 Red Hat
-
- Alpha/OSF Foreign Function Interface